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hi-3584a arinc 429 3.3v serial transmitter and dual receiver with high-speed interface (ds3584a rev. c) 7/13 0 pin configurations (top view) (see page 13 for additional pin configuration) general description the hi-3584a from holt integrated circuits is a silicon gate cmos device for interfacing a 16-bit parallel data bus to the arinc 429 serial bus. the hi-3584a design offers a high- speed host cpu interface compared with the earlier hi- 3584 product. the device provides two receivers each with label recognition, a 32 by 32 fifo, and an analog line receiver. up to 16 labels may be programmed for each receiver. the independent transmitter also has a 32 by 32 fifo the status of all three fifos can be monitored using the external status pins or by polling the hi-3584a?s status register. other features include a programmable option of data or parity in the 32nd bit, and the ability to unscramble the 32 bit word. also, versions are available with different values of input resistance to allow users to more easily add external lightning protection circuitry. the 16-bit parallel data bus exchanges the 32-bit arinc data word in two steps when either loading the transmitter or interrogating the receivers. the databus and all control signals are cmos and ttl compatible. the hi-3584a applies the arinc protocol to the receivers and transmitter. timing is based on a 1 megahertz clock. . additional interface circuitry such as the holt hi-8570 or hi-8571 is required to translate the transmitter?s 3.3 volt logic outputs to arinc 429 drive levels. july 2013 features ? arinc specification 429 compatible ? dual receiver and transmitter interface ? programmable label recognition ? 32 x 32 fifos each receiver and transmitter ? status register ? data scramble control ? 32nd transmit bit can be data or parity ? self test mode ? low power ? industrial & extended temperature ranges ? 3.3v logic supply operation ? analog line receivers connect directly to arinc bus ? on-chip 16 label memory for each receiver ? independent data rate selection for transmitter and each receiver hi-3584apqi hi-3584apqt & hi-3584apqm 52 - 51 - rin2b 50 - rin2a 49 - rin1b 48 - rin1a 47 - vdd 46 - n/c 45 - n/c 44 - 43 - txclk 42 - clk 41 - 40 - n/c d/r1 mr rsr 39 - n/c 38 - 37 - entx 36 - n/c 35 - 34 - 429do 33 - n/c 32 - 31 - 30 - tx/r 29 - 28 - 27 - bd00 cwstr fft hft pl2 pl1 429do bd10 - 14 bd09 - 15 bd08 - 16 bd07 - 17 bd06 - 18 n/c-19 -20 n/c-21 bd05 - 22 bd04 - 23 bd03 - 24 bd02 - 25 bd01 - 26 gnd ff1 hf1 d/r2 ff2 hf2 en1 en2 -1 -2 -3 -4 -5 sel - 6 -7 -8 bd15 - 9 bd14 - 10 bd13 - 11 bd12 - 12 bd11 - 13 52 - pin plastic quad flat pack (pqfp) 64 - n/c 63 - rin2b 62 - rin2a 61 - rin1b 60 - rin1a 59 - n/c 58 - vdd 57 - vdd 56 - vdd 55 - n/c 54 - n/c 53 - 51 mr rsr 52 - txclk - clk 50 - 49 - n/c 48 47 46 - 45 - n/c 44 - n/c 43 - n/c 42 - n/c 41 40 - 39 - 38 - tx/r 37 - 36 - 35 - 34 - bd01 - - entx - 429do bd00 33 - n/c cwstr 429do fft hft pl2 pl1 n/c - 17 bd10 - 18 bd09 - 19 bd08 - 20 bd07 - 21 -22 -23 n/c - 24 -25 -26 -27 bd05 - 28 bd04 - 29 bd06 n/c n/c n/c bd03 - 30 bd02 - 31 n/c - 32 gnd n/c - 1 -2 -3 -4 -5 -6 -7 sel - 8 -9 -10 n/c - 11 bd15 - 12 d/r1 ff1 d/r2 ff2 hf2 en1 en2 hf1 bd14 - 13 bd13 - 14 bd12 - 15 bd11 - 16 (note: all 3 vdd pins be connected to the same 3.3v supply) must 64 - pin plastic 9mm x 9mm chip-scale package hi-3584apci hi-3584apct & hi-3584apcm see note below applications ? avionics data communication ? serial to parallel conversion ? parallel to serial conversion holt integrated circuits www.holtic.com (
pin descriptions hi-3584a signal function description vdd power +3.3v % (all three vdd pins on the chip-scale package be connect to the same supply) bd05 i/o data bus bd04 i/o data bus bd03 i/o data bus bd02 i/o data bus must 5 rin1a input arinc receiver 1 positive input rin1b input arinc receiver 1 negative input rin2a input arinc receiver 2 positive input rin2b input arinc receiver 2 negative input output receiver 1 data ready flag output fifo full receiver 1 output fifo half full, receiver 1 output receiver 2 data ready flag output fifo full receiver 2 output fifo half full, receiver 2 sel input receiver data byte selection (0 = byte 1) (1 = byte 2) input data bus control, enables receiver 1 data to outputs input data bus control, enables receiver 2 data to outputs if is high bd15 i/o data bus bd14 i/o data bus bd13 i/o data bus bd12 i/o data bus bd11 i/o data bus bd10 i/o data bus bd09 i/o data bus bd08 i/o data bus bd07 i/o data bus bd06 i/o data bus gnd power 0 v bd01 i/o data bus bd00 i/o data bus input latch enable for byte 1 entered from data bus to transmitter fifo. input latch enable for byte 2 entered from data bus to transmitter fifo. must follow tx/r output transmitter ready flag. goes low when arinc word loaded into fifo. goes high after transmission and fifo empty. output transmitter fifo half full output transmitter fifo full 429do output ?ones? data output from transmitter output ?zeros? data output from transmitter entx input enable transmission input clock for control word register input read status register if sel=0, read control register if sel=1 clk input master clock input tx clk output transmitter clock equal to master clock (clk), divided by either 10 or 80. input master reset, active low d/r1 ff1 hf1 d/r2 ff2 hf2 en1 en2 en1 pl1 pl2 pl1. hft fft 429do cwstr rsr mr holt integrated circuits 2
control word register the hi-3584a contains a 16-bit control register which is used to configure the device. the control register bits cr0 - cr15 are loaded from bd00 - bd15 when is pulsed low. the con- trol register contents are output on the databus when sel = 1 and is pulsed low. each bit of the control register has the follow- ing function: cwstr rsr status register the hi-3584a contains a 9-bit status register which can be interro- gated to determine the status of the arinc receivers, data fifos and transmitter. the contents of the status register are output on bd00 - bd08 when the pin is taken low and sel = 0. unused bits are output as zeros. the following table defines the status reg- ister bits. rsr sr bit function state description sr0 data ready 0 receiver 1 fifo empty 1 receiver 1 fifo contains valid data resets to zero when all data has been read. pin is the inverse of this bit (receiver 1) sr1 fifo half full 0 receiver 1 fifo holds less than 16 (receiver 1) words 1 receiver 1 fifo holds at least 16 words. pin is the inverse of this bit. sr2 fifo full 0 receiver 1 fifo not full (receiver 1) 1 receiver 1 fifo full. to avoid data loss, the fifo must be read within one arinc word period. pin is the inverse of this bit sr3 data ready 0 receiver 2 fifo empty (receiver 2) 1 receiver 2 fifo contains valid data resets to zero when all data has been read. pin is the inverse of this bit sr4 fifo half full 0 receiver 2 fifo holds less than 16 (receiver 2) words 1 receiver 2 fifo holds at least 16 words. pin is the inverse of this bit. sr5 fifo full 0 receiver 2 fifo not full (receiver 2) 1 receiver 2 fifo full. to avoid data loss, the fifo must be read within one arinc word period. pin is the inverse of this bit sr6 transmitter fifo 0 transmitter fifo not empty empty 1 transmitter fifo empty. sr7 transmitter fifo 0 transmitter fifo not full full 1 transmitter fifo full. pin is the inverse of this bit. sr8 transmitter fifo 0 transmitter fifo contains less than half full 16 words 1 transmitter fifo contains at least 16 words. pin is the inverse of this bit. d/r1 hf1 ff1 d/r2 hf2 ff2 fft hft cr bit function state description cr0 receiver 1 0 data rate = clk/10 select 1 data rate = clk/80 data clock cr1 label memory 0 normal operation read / write 1 load 16 labels using / read 16 labels using / cr2 enable label 0 disable label recognition recognition (receiver 1) 1 enable label recognition cr3 enable label 0 disable label recognition recognition (receiver 2) 1 enable label recognition cr4 enable 0 transmitter 32nd bit is data 32nd bit as parity 1 transmitter 32nd bit is parity cr5 self test 0 the 429do and digital outputs are internally connected to the receiver logic inputs 1 normal operation cr6 receiver 1 0 receiver 1 decoder disabled decoder 1 arinc bits 9 and 10 must match cr7 and cr8 cr7 - - if receiver 1 decoder is enabled, the arinc bit 9 must match this bit cr8 - - if receiver 1 decoder is enabled, the arinc bit 10 must match this bit cr9 receiver 2 0 receiver 2 decoder disabled decoder 1 arinc bits 9 and 10 must match cr10 and cr11 cr10 - - if receiver 2 decoder is enabled, the arinc bit 9 must match this bit cr11 - - if receiver 2 decoder is enabled, the arinc bit 10 must match this bit cr12 invert 0 transmitter 32nd bit is odd parity transmitter parity 1 transmitter 32nd bit is even parity cr13 transmitter 0 data rate=clk/10, o/p slope=1.5us data clock select 1 data rate=clk/80, o/p slope=10us cr14 receiver 2 0 data rate=clk/10 data clock select 1 data rate=clk/80 cr15 data 0 scramble arinc data format 1 unscramble arinc data pl1 pl2 en1 en2 429do functional description hi-3584a holt integrated circuits 3
v dd gnd gnd rin1b or rin2b rin1a or rin2a differential amplifiers ones comparators null zeroes v dd figure 1. arinc receiver input functional description (cont.) the receivers arinc bus interface figure 1 shows the input circuit for each receiver. the arinc 429 specification requires the following detection levels: one +6.5 volts to +13 volts null +2.5 volts to -2.5 volts zero -6.5 volts to -13 volts state differential voltage byte 2 data bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 arinc 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 bit cr15=0 arinc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit cr15=1 parity parity sdi sdi label label sdi sdi label label label label label label label label label label label label label label arinc 429 data format control register bit cr15 is used to control how individual bits in the received or transmitted arinc word are mapped to the hi-3584a data bus during data read or write operations. the following table describes this mapping: data bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 arinc 13 12 11 10 9 31 30 32 12345678 bit cr15=0 byte 1 arinc 16 15 14 13 12 11 10 987654321 bit cr15=1 the hi-3584a guarantees recognition of these levels with a common mode voltage with respect to gnd less than 4v for the worst case condition (3.0v supply and 13v signal level). the tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the arinc signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. receiver logic operation bit timing bit rate pulse rise time pulse fall time pulse width figure 2 shows a block diagram of the logic section of each receiver. the arinc 429 specification contains the following timing specifi- cation for the received data: 100k bps 1% 12k -14.5k bps 1.5 0.5 sec 10 5 sec 1.5 0.5 sec 10 5 sec 5 sec 5% 34.5 to 41.7 sec the hi-3584a accepts signals that meet these specifications and re- jects signals outside the tolerances. the way the logic operation achieves this is described below: high speed low speed 3. each data bit must follow its predecessor by not less than 8 samples and no more than 12 samples. in this manner the bit rate is checked. with exactly 1mhz input clock frequency, the acceptable data bit rates are as follows: 83k bps 10.4k bps 125k bps 15.6k bps 4. the word gap timer samples the null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. if the null is present, the word gap counter is incremented. a count of 3 will enable the next reception. high speed low speed data bit rate min data bit rate max 1. key to the performance of the timing checking logic is an ac- curate 1mhz clock source. less than 0.1% error is recom- mended. 2. the sampling shift registers are 10 bits long and must show three consecutive ones, zeros or nulls to be considered valid data. additionally, for data bits, the one or zero in the upper bits of the sampling shift registers must be followed by a null in the lower bits within the data bit time. for a null in the word gap, three consecutive nulls must be found in both the upper and lower bits of the sampling shift register. in this manner the mini- mum pulse width is guaranteed. hi-3584a holt integrated circuits 4
fifo load control sel en control bit / r/w control 32 to 16 driver 32 bit shift register to pins controlbits cr0, cr14 clock option clock clk bit counter and end of sequence parity check 32nd bit data bit clock word gap word gap timer bit clock end start sequence control error clock error detection shift register shift register null zeros shift register ones eos figure 2. receiver block diagram label / decode compare 16x8 label memory 32x32 fifo d/r ff mux contro l control bits hf functional description (cont.) hi-3584a 0 x 0 x load fifo 1 no 0 x ignore data 1 yes 0 x load fifo 0 x 1 no ignore data 0 x 1 yes load fifo 1 yes 1 no ignore data 1 no 1 yes ignore data 1 no 1 no ignore data 1 yes 1 yes load fifo cr2(3) arinc word cr6(9) arinc word fifo matches bits 9,10 label match cr7,8 (10,11) receiver parity odd parity received even parity received the 32nd bit of received arinc words stored in the receive fifo is used as a parity flag indicating whether good odd parity is received from the incoming arinc word. the parity bit is reset to indicate correct parity was received and the resulting word is then written to the receive fifo. the receiver sets the 32nd bit to a ?1?, indicating a parity error and the resulting word is then written to the receive fifo. therefore, the 32nd bit retrieved from the receiver fifo will always be ?0? when valid (odd parity) arinc 429 words are received. retrieving data once 32 valid bits are recognized, the receiver logic generates an end of sequence (eos). depending upon the state of control register bits cr2-cr11, the received arinc 32-bit word is then checked for correct decoding and label matching before being loaded into the 32 x 32 receive fifo. arinc words which do not meet the necessary 9th and 10th arinc bit or label matching are ignored and are not loaded into the receive fifo. the following table describes this operation. holt integrated circuits 5
reading labels after the write that changes cr1 from 0 to 1, the next 16 data reads of the selected receiver ( taken low) are labels. is used to read labels for receiver 1, and to read labels for receiver 2. label data is presented on bd00 - bd07. when writing to, or reading from the label memory, sel must be a one, all 16 locations should be accessed, and cr1 must be written to zero before returning to normal operation. label recognition must be disabled (cr2/3=0) during the label read sequence. en en1 en2 transmitter fifo operation the fifo is loaded sequentially by first pulsing to load byte 1 and then to load byte 2. the control logic automatically loads the 31 bit word (or 32 bit word if cr4=0) in the next available position of the fifo. if tx/r, the transmitter ready flag is high (fifo empty), then up to 32 words, each 31 or 32 bits long, may be loaded. if tx/r is low, then only the available positions may be loaded. if all 32 positions are full, the flag is asserted and the fifo ignores further attempts to load data. a transmitter fifo half-full flag is provided. when the transmit fifo contains less than 16 words, is high, indicating to the system microprocessor that a 16 arinc word block write sequence can be initiated. in normal operation (cr4=1), the 32nd bit transmitted is a parity bit. odd or even parity is selected by programming control register bit cr12 to a zero or one. if cr4 is programmed to a 0, then all 32-bits of data loaded into the transmitter fifo are treated as data and are transmitted. pl1 pl2 fft hft hft label recognition the chip compares the incoming label to the stored labels if label recognition is enabled. if a match is found, the data is processed. if a match is not found, no indicators of receiving arinc data are presented. note that 00(hex) is treated in the same way as any other label value. label bit significance is not changed by the status of control register bit cr15. label bits bd00-bd07 are always compared to received arinc bits 1 -8 respectively. after a write that takes cr1 from 0 to 1, the next 16 writes of data ( pulsed low) load label data into each location of the label memory from the bd00 - bd07 pins. the pin is used to write label data for receiver 1 and for receiver 2. loading labels pl pl1 pl2 note that arinc word reception is suspended during the label memory write sequence. once a valid arinc word is loaded into the fifo, then eos clocks the data ready flag flip flop to a "1", or (or both) will go low. the data flag for a receiver will remain low until arinc bytes from that receiver are retrieved and the fifo is empty. this is accomplished by first activating with sel, the byte selector, low to retrieve the first byte and then activating with sel high to retrieve the second byte. retrieves data from receiver 1 and retrieves data from receiver 2. up to 32 arinc words may be loaded into each receiver?s fifo. the ( ) pin will go low when the receiver 1 (2) fifo is full. failure to retrieve data from a full fifo will cause the next valid arinc word received to overwrite the existing data in fifo location 32. a fifo half full flag ( ) goes low if the fifo contains 16 or more received arinc words. the ( ) pin is intended to act as an interrupt flag to the system?s external microprocessor, allowing a 16 word data retrieval routine to be performed, without the user needing to continually poll the hi- 3584a?s status register bits. d/r1 d/r2 en en en1 en2 ff1 ff2 hf1 hf2 hf1 hf2 both cr4,12 figure 3. transmitter block diagram data clock cr13 pl1 pl2 clk tx clk parity generator data and null timer sequencer bit and word gap counter start sequence word counter and fifo control increment word count data clock divider fifo loading sequencer 429do 429do 32 x 32 fifo 32 bit parallel load shift register bit clock word clock address load data bus tx/r entx hft fft functional description (cont.) hi-3584a holt integrated circuits 6
data transmission repeater operation hi-3584a-15 master reset ( ) when entx goes high, enabling transmission, the fifo positions are incremented with the top register loading into the data transmission shift register. within 2.5 data clocks the first data bit appears at 429do and . the 31 or 32 bits in the data transmission shift register are presented sequentially to the outputs in the arinc 429 format with the following timing: arinc data bit time 10 clocks 80 clocks data bit time 5 clocks 40 clocks null bit time 5 clocks 40 clocks word gap time 40 clocks 320 clocks the word counter detects when all loaded positions have been transmitted and sets the transmitter ready flag, tx/r, high. repeater mode of operation allows a data word that has been received by the hi-3584a to be placed directly into the transmitter fifo. repeater operation is similar to normal receiver operation. in normal operation, either byte of a received data word may be read from the receiver latches first by use of sel input. during repeater operation however, the lower byte of the data word must be read first. this is necessary because, as the data is being read, it is also being loaded into transmitter fifo which is always loaded with the lower byte of the data word first. signal flow for repeater operation is shown in the timing diagrams section. please refer to the holt an-300 application note for additional information and recommendations on lightning protection of holt line drivers and line receivers. on a master reset data transmission and reception are immediately terminated, all three fifos are cleared as are the fifo flags at the device pins and in the status register. the control register is not affected by a master reset. 429do high speed low speed transmitter parity self test system operation the parity generator counts the ones in the 31-bit word. if control register bit cr12 is set low, the 32nd bit transmitted will make parity odd. if the control bit is, high the parity is even. setting cr4 to a zero bypasses the parity generator, and allows 32 bits of data to be transmitted. if control register bit cr5 is set low, the transmitter serial output data are internally connected to each of the two receivers, bypassing the analog interface circuitry. data is passed unmodi- fied to receiver 1 and inverted to receiver 2. the serial data from the transmitter is always present on the 429do and outputs regardless of the state of cr5. the two receivers are independent of the transmitter. therefore, control of data exchanges is strictly at the option of the user. the only restrictions are: 1. the received data will be overwritten if the receiver fifo is full and at least one location is not retrieved before the next complete arinc word is received. 2. the transmitter fifo can store 32 words maximum and ignores attempts to load additional data if full. 429do the hi-3584a-15 option is similar to the hi-3584a with the excep- tion that it allows an external 15 kohm resistor to be added in se- ries with each arinc input without affecting the arinc input thresholds. this option is especially useful in applications where lightning protection circuitry is also required. each side of the arinc bus must be connected through a 15 kohm series resistor in order for the chip to detect the correct arinc levels. the typical 10 volt differential signal is translated and input to a window comparator and latch. the comparator levels are set so that with the external 15 kohm resistors, they are just below the standard 6.5 volt minimum arinc data threshold and just above the standard 2.5 volt maximum arinc null threshold. the hi-3584a may be operated at clock frequencies beyond that required for arinc compliant operation. for operation at master clock (clk) frequencies up to 5mhz, please contact holt appli- cations engineering. high speed operation mr functional description (cont.) hi-3584a holt integrated circuits 7
timing diagrams loading control word cwhld t cwset t cwstr t data bus cwstr valid transmitter operation pl2 dwset t dwhld t tx/r t dwhld t pl12 t pl t data bus pl1 tx/r, , hft fft byte 2 valid pl t pl12 t dwset t byte 1 valid selen t ensel t selen t byte 1 dataen t endata t readen t receiver operation d/r hf ff ,, arinc data sel en data bus bit 31 bit 32 selen t d/r t dataen t d/ren t end/r t en t ensel t endata t endata t enen t don't care byte 1 valid byte 2 valid data rate - example pattern 429 data arinc bit 429 data null data data data null null word gap bit 1 next word bit 32 bit 31 bit 30 hi-3584a clk clken t clken t plcyc t holt integrated circuits 8
label memory read sequence cwstr / en1 en2 data bus set cr1=1 label #1 label #16 set cr1=0 cwstr t cwset t cwhld t endata t label #2 dataen t readen t label memory load sequence cwstr / pl1 pl2 data bus set cr1=1 label #1 label #2 label #16 set cr1=0 cwstr t cwset t cwhld t dwset t dwhld t pl t label t control register read cycle byte select sel rsr data bus selen t dataen t ensel t endata t don't care don't care data valid status register read cycle byte select sel rsr data bus selen t dataen t ensel t endata t don't care don't care data valid timing diagrams (cont.) hi-3584a holt integrated circuits 9
timing diagrams (cont.) repeater operation timing don't care rin d/r en pl1 pl2 sel txr entx 429do 429do bit 32 don't care d/r t en t d/ren t enen t en t end/r t selen t ensel t enpl t plen t selen t ensel t enpl t plen t tx/r t tx/ren t endat t entx/r t dtx/r t null t bit 1 bit 32 one zero null transmitting data arinc bit pl2 entx 429do 429do txr pl2en t endat t dtx/r t entx/r t data bit 2 arinc bit data bit 32 null one null arinc bit data bit 1 hi-3584a holt integrated circuits 10
absolute maximum ratings dc electrical characteristics limits parameter conditions unit symbol differential input voltage: one v common mode voltage 6.5 10.0 13.0 v (rin1a to rin1b, rin2a to rin2b) zero v less than 4v with -13.0 -10.0 -6.5 v null v with respect to gnd -2.5 0 2.5 v input resistance: differential r 12 80 k to gnd r 12 45 k to v r 12 45 k input current: input sink i 200 a input source i -450 a input capacitance: differential c 20 pf (guaranteed but not tested) to gnd c 20 pf to v c 20 pf input voltage: input voltage hi v 70% v input voltage lo v 30% v input current: input sink i 1.5 a input source i -1.5 a input voltage: input voltage hi v 70% v input voltage lo v 30% v input current: input sink i 1.5 a input source i -1.5 a input capacitance: 15 pf (guaranteed but not tested) min typ max arinc inputs - pins rin1a, rin1b, rin2a, rin2b bi-directional inputs - pins bd00 - bd15 other inputs ih il nul i g dd h ih il i g dd h ih il ih il ih il ih il (rin1a to rin1b, rin2a to rin2b) pull-down current (test pin) i 330 a pull-up current ( pin) i -330 a c output voltage: logic "1" output voltage v i = -100a v logic "0" output voltage v i = 1.0ma v output current: output sink i v = 0.4v 1.6 ma (all outputs & bi-directional pins) output source i v = v - 0.4v -1.0 ma output capacitance: c 15 pf vdd i 3.5 7 ma dd dd pd pu i oh oh ol ol 10%vdd ol out oh out dd o dd rsr outputs operating supply current vdd - 0.2v v = 3.3v, gnd = 0v, ta = operating temperature range (unless otherwise specified). dd supply voltages v ........................................... -0.3v to +4v voltage at pins rin1a, rin1b, rin2a, rin2b ... -120v to +120v voltage at any other pin ............................... -0.3v to v +0.3v solder temperature (reflow) ............................................ 2 dd dd 60c power dissipation at 25c .......................................... 500 mw dc current drain per pin .............................................. 10ma operating temperature range (industrial): .... -40c to +85c (extended): .. -55c to +125c storage temperature range ........................ -65c to +150c note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. hi-3584a holt integrated circuits 11
ac electrical characteristics vdd = 3.3v, gnd = 0v, ta = oper. temp. range and fclk=1mhz 0.1% with 60/40 duty cycle + hi-3584a repeater operation timing delay - low to low t 0 ns en pl enpl hold - high to high t 0 ns delay - tx/r low to entx high t 0 ns t 175 ns 1% pl en plen tx/ren mr master reset pulse width arinc data rate and bit timing limits parameter symbol units min typ max control word timing receiver fifo and label read timing transmitter fifo and label write timing transmission timing pulse width - t 25 ns setup - data bus valid to high t 25 ns hold - high to data bus hi-z t 5 ns delay - start arinc 32nd bit to low: high speed t 16 s low speed t 128 s delay - low to low t 0 ns delay - high to high t 25 ns setup - sel to low t 0 ns hold - sel to high t 10 ns delay - low to data bus valid t 50 ns delay - high to data bus hi-z t 20 ns pulse width - or t 50 ns spacing - high to next low (same arinc word) t 70 ns spacing - high to next low (next arinc word) t 70 ns 25 ns pulse width - or t 30 ns setup - data bus valid to high t 30 ns hold - high to data bus hi-z t 10 ns spacing - or t 40 ns spacing - spacing between label write pulses t 40 ns delay - high to tx/r low t 30 ns spacing - high to entx high t 0 s delay - 32nd arinc bit to tx/r high t 50 ns spacing - tx/r high to entx low t 0 ns cwstr cwstr cwstr d/r d/r en en d/r en en en en en1 en2 en en en en pl1 pl2 pl pl pl1 pl2 pl2 pl2 cwstr cwset cwhld d/r d/r d/ren end/r selen ensel endata dataen en enen readen pl dwset dwhld pl12 label tx/r pl2en dtx/r entx/r clk high separation from second pulse high (sel is high) t rising to rising t t -10 ns delay - entx high to 429do or : high speed t 25 s delay - entx high to 429do or : low speed t 200 s en pl1 pl2 429do 429do clken plcyc endat endat clk holt integrated circuits 12
ordering information additional hi-3584a pin configuration 7- 6 - rin2b 5 - rin2a 4 - rin1b 3 - rin1a 2 - vdd 1 - n/c 52 - n/c 51 - 50 - txclk 49 - clk 48 - 47 - n/c d/r1 mr rsr 46 - n/c 45 - 44 - entx 43 - n/c 42 - 41 - 429do 40 - n/c 39 - 38 - 37 - tx/r 36 - 35 - 34 - bd00 cwstr fft hft pl2 pl1 429do bd10 - 21 bd09 - 22 bd08 - 23 bd07 - 24 bd06 - 25 n/c-26 gnd-27 n/c-28 bd05 - 29 bd04 - 30 bd03 - 31 bd02 - 32 bd01 - 33 ff1 hf1 d/r2 ff2 hf2 en1 en2 -8 -9 -10 -11 -12 sel - 13 -14 -15 bd15 - 16 bd14 - 17 bd13 - 18 bd12 - 19 bd11 - 20 hi-3584acji hi-3584acjt & hi-3584acjm 52 - pin cerquad j-lead (see page 1 for additional pin configurations) hi - 3584a - xxxx xx part package number description cj 52 pin j-lead cerquad (52u) not available pb-free pc 64 pin plastic chip-scale lpcc (64pcs) pq 52 pin plastic quad flat pack pqfp (52ptqs) part temperature burn number range flow in i -40c to +85c i no t -55c to +125c t no m -55c to +125c m yes part package number description blank tin / lead (sn / pb) solder f 100% matte tin (pb-free rohs compliant) no dash number 35k ohm 0 -15 20k ohm 15k ohm part input series resistance number built-in required externally hi-3584a holt integrated circuits 13
hi-3584a revision history p/n rev date description of change ds3584a new 04/28/09 initial release a 04/27/10 added clken to timing parameters. b 06/29/10 added plcyc to timing parameters. c 07/25/13 updated receiver parity function, qfn and pqfp package drawing, timing parameter tselen and solder temperature parameters. remove note on heat sink connection for qfn package. update voltage at arinc input pins from +/-29v to +/-120v holt integrated circuits 14
hi-3584a package dimensions 52-pin j-lead cerquad inches (millimeters) package type: 52u bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .019 .002 (.483 .051) 8 7 1 52 47 .788 (20.0) .720 .010 (18.29 .25) .750 .007 (19.05 .18) .190 (4.826) max
.050 (1.27) bsc sq. max 52-pin plastic quad flat pack (pqfp) inches (millimeters) package type: 52pqs d etail a see detail a 0 7 .520 (13.2) bsc sq .394 (10.0) bsc sq .063 (1.6) typ .008 (.20) min .005 (.13) r min r min .005 (.13) .0256 (.65) bsc .012 .004 (.310 .09) .035 .006 (.88 .15) .079 .008 (2.0 .20) .106 (2.7) max. bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) holt integrated circuits 15
hi-3584a package dimensions 64-pin plastic chip-scale package (qfn) inches (millimeters) package type: 64pcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .354 (9.00) bsc .039 (1.00) max .008 (0.20) typ .0197 (0.50) bsc .010 (0.25) typ .016 .002 (0.40 05) . .268 .039 (6.80 ) .05 .268 .039 (6.80 ) .05 bottom view top view .354 (9.00) bsc electrically isolated heat sink pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. holt integrated circuits 16

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